1. Field of the Invention
The present invention generally relates to an information processing apparatus, and more particularly, to a multifunctional information processing apparatus having a virtual storage system in which plural processes can efficiently share data.
2. Description of the Related Art
An information processing apparatus such as a personal computer and an image forming apparatus can provide various information processing functions to a user by executing one or more software programs each corresponding to a function. In the case of a conventional information processing apparatus, when one or more software programs are executed simultaneously and a plurality of processes are consequently created in parallel, each process separately reserves a memory region.
Especially, an image forming apparatus is an example of such an information processing apparatus. The recent image forming apparatuses include integrated systems of a digital copier, a printer, a scanner, and a facsimile (hereinafter referred to as a multifunctional apparatus). The multifunctional apparatus is provided with a display unit, a printing unit, and an image capture unit in the system, and is further provided with software programs corresponding to the functions of a digital copier, a printer, a scanner, or a facsimile. A user can use the multifunctional apparatus as a digital copier, a printer, a scanner, or a facsimile by switching the software program.
The multifunctional apparatus is provided with separate software programs that cause the system (multifunctional apparatus) to function as a printer, a digital copier, a facsimile, and a scanner. When executed, the separate software programs create processes. The created processes separately reserve memory regions and manage the memory regions independently.
By the way, the software programs executed by the information processing apparatus are usually operated on an operating system (OS), and the OS manages memory regions of the information processing apparatus. An OS that enables the system to execute a plurality of processes simultaneously (multi-processing OS) usually manages the memory region of the system using, for example, virtual addressing in which each process is provided with a different virtual memory space.
The virtual addressing protects data stored in a virtual memory space of a process from accesses from another process using “paging”. The paging divides the virtual address space provided to a process and the physical address space of the physical memory into pages each having the same predetermined memory size specific to a processor model. The paging manages the corresponding relationship between the page of the virtual address space and the page of the physical address space, and translates a virtual address into a physical address.
The paging manages the above corresponding relationship using a page table. Each process to which a virtual address space is provided requires a page table.
Since paging requires translation from a virtual address to a physical address for each memory access, the translation needs to be performed by hardware so as not to lower the performance of the system. The translation is usually done by the memory management unit (MMU) of a processor. The architecture of MMUs is different for each processor model.
For example, the MMU of a processor model, if the physical address of a page table (of a process) is set in a control resister, automatically checks the page table. When the process is switched to another, the physical address of the other page table of the other process is set in the control resister.
The MMU of another processor model does not automatically check the page table, but the MMU checks a translation look aside buffer (TLB) that is a translation table provided inside the processor. If there is no entry of the virtual address to which the process accesses in TLB, a TLB exception error occurs. In this case, a software program (handler) searches the page table after the occurrence of the TLB exception error. If necessary, the software program adds an entry to the TLB.
As described above, address management by paging requires hardware to accelerate speed. An address management method called “demand paging”, however, inherits the following problems.
When a process is created, no physical memory is allocated to the process, and all the entries of a page table are set invalid. When executed, the process accesses the memory, and a page table exception error occurs. The handler of this page table exception error reserves the physical memory and creates the contents of the page table.
Accordingly, even if the physical memory is still available, the process has to wait for the handler to set the page table (the process suffers from processing overhead). This overhead matters especially in the case of information processing such as image forming that requires a large memory.
The address of the physical memory corresponding to the virtual memory is set up in the page table so that the processor can manage the physical memory flexibly. In this case, however, data stored in a continuous region of the virtual address space may be stored in separate regions of the physical address space. That is, the data stored in the physical address space become discontinuous. Consequently, when the data need to be exchanged between the memory and another element of the system by direct memory access (DMA), the discontinuity of the data degrades the efficiency of data exchange.
Japanese Laid-open Patent Application No. 7-160583 discloses a technique to share the page table. Japanese Laid-open Patent Application No. 6-58649 discloses a technique in which a segment of the virtual memory space is divided into a common region and a proper region. Neither technique, however, can reduce the overhead caused by memory accesses.
MIPS (trade mark) CPU, for example, employs architecture in which physical memory is allocated to the direct mapping regions of all processes using entries of TLB that are fixedly used. In such a case, a process B may erroneously write data in a direct mapping region that only a process A is permitted to access due to a bug in a computer program. The bug may not be easily identifiable, and the causal analysis of the error may take a long time.
The direct mapping region that only the process A is permitted to access is a region that is allocated to the process A using function (of MEM-P0) for allocating the direct mapping region only to the process A using a system call. When the process B writes data in this region, the process B ends abnormally. According to this arrangement, the error becomes easy to identify.
Additionally, the use of the direct mapping region brings the following effect. When a page exception occurs, a virtual memory processing unit of the operating system is executed. According to the execution of the virtual memory processing unit of the operating system, when a large memory needs to be accessed, the overhead on the CPU is great. The use of the direct mapping region can eliminate the overhead on the CPU.